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<p class=MsoPlainText>The comments from the switch_x64_masm.masm really only are
valid on windows.<o:p></o:p></p>
<p class=MsoPlainText>To know what to do on linux, we need to know the x64 ABI
that linux employs, which is bound to be different from what win64 uses.<o:p></o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText>I found this document:<o:p></o:p></p>
<p class=MsoPlainText><a href="http://www.x86-64.org/documentation/abi.pdf">http://www.x86-64.org/documentation/abi.pdf</a><o:p></o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText>And on page 14, it says this:<o:p></o:p></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i><o:p> </o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>3.2.1 Registers and the
Stack Frame<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>The AMD64 architecture
provides 16 general purpose 64-bit registers. In addition<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>the architecture provides
16 SSE registers, each 128 bits wide and 8 x87 floating<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>point registers, each 80
bits wide. Each of the x87 floating point registers may be<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>referred to in MMX/3DNow!
mode as a 64-bit register. All of these registers are<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>global to all procedures
active for a given thread.<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>This subsection discusses
usage of each register. Registers %rbp, %rbx and<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>%r12 through %r15
“belong” to the calling function and the called function is<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>required to preserve their
values. In other words, a called function must preserve<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>these registers’
values for its caller. Remaining registers “belong” to the called<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>function.5 If a calling
function wants to preserve such a register value across a<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>function call, it must save
the value in its local stack frame.<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>The CPU shall be in x87
mode upon entry to a function. Therefore, every<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>function that uses the MMX
registers is required to issue an emms or femms<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>instruction after using MMX
registers, before returning or calling another function.<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>6 The direction flag DF in
the %rFLAGS register must be clear (set to “forward”<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>direction) on function
entry and return. Other user flags have no specified role in<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>the standard calling
sequence and are not preserved across calls.<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>The control bits of the
MXCSR register are callee-saved (preserved across<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>calls), while the status
bits are caller-saved (not preserved). The x87 status word<o:p></o:p></i></p>
<p class=MsoPlainText style='margin-left:36.0pt'><i>register is caller-saved,
whereas the x87 control word is callee-saved.<o:p></o:p></i></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText>From this it seems that we must save rbp, rbx and r12-r15,
plus the mxcsr register.<o:p></o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText>K<o:p></o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText><o:p> </o:p></p>
<p class=MsoPlainText>> -----Original Message-----<o:p></o:p></p>
<p class=MsoPlainText>> From: stackless-bounces@stackless.com
[mailto:stackless-<o:p></o:p></p>
<p class=MsoPlainText>> bounces@stackless.com] On Behalf Of Richard Tew<o:p></o:p></p>
<p class=MsoPlainText>> Sent: Wednesday, May 09, 2007 07:04<o:p></o:p></p>
<p class=MsoPlainText>> To: Alec Flett<o:p></o:p></p>
<p class=MsoPlainText>> Cc: Stackless mailing list<o:p></o:p></p>
<p class=MsoPlainText>> Subject: Re: [Stackless] Stackless Python for Python
2.5.1<o:p></o:p></p>
<p class=MsoPlainText>> <o:p></o:p></p>
<p class=MsoPlainText>> On 5/8/07, Alec Flett <alecf@flett.org> wrote:<o:p></o:p></p>
<p class=MsoPlainText>> > So what is the state of the amd64 support? I
saw a lot of stuff<o:p></o:p></p>
<p class=MsoPlainText>> exchanged a<o:p></o:p></p>
<p class=MsoPlainText>> > few weeks back with Hieu but I wasn't really
sure of the conclusion.<o:p></o:p></p>
<p class=MsoPlainText>> <o:p></o:p></p>
<p class=MsoPlainText>> Exactly what I said in the email you quoted:<o:p></o:p></p>
<p class=MsoPlainText>> <o:p></o:p></p>
<p class=MsoPlainText>> "The only remaining known issue is that the
amd64 linux platform is not<o:p></o:p></p>
<p class=MsoPlainText>> supported at this time. This involves a large
amount of effort which<o:p></o:p></p>
<p class=MsoPlainText>> I have not as yet had time for."<o:p></o:p></p>
<p class=MsoPlainText>> <o:p></o:p></p>
<p class=MsoPlainText>> Shouldn't people on AMD64 platforms be able to
compile for x86 still<o:p></o:p></p>
<p class=MsoPlainText>> and use Stackless that way in the meantime?<o:p></o:p></p>
<p class=MsoPlainText>> <o:p></o:p></p>
<p class=MsoPlainText>> Richard.<o:p></o:p></p>
<p class=MsoPlainText>> <o:p></o:p></p>
<p class=MsoPlainText>> _______________________________________________<o:p></o:p></p>
<p class=MsoPlainText>> Stackless mailing list<o:p></o:p></p>
<p class=MsoPlainText>> Stackless@stackless.com<o:p></o:p></p>
<p class=MsoPlainText>> http://www.stackless.com/mailman/listinfo/stackless<o:p></o:p></p>
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